
// File RTSHDR

// Version:  D2.1

// Header file for BCPL run-time support on DEC VAX-11 under VMS

// Copyright R.D. Eager   University of Kent   MCMLXXXVIII


MANIFEST $(
svsize     = 30    // Size of system vector

sv.base    = -svsize  // Base of system vector
$)

GLOBAL $(   // System vector
sv.undefglob : sv.base+00   // Contents of undefined globals
sv.tracep    : sv.base+01   // Trace pointer
sv.traceb    : sv.base+02   // Base of trace buffer (byte address)
sv.tbsize    : sv.base+03   // Size of trace buffer

sv.curin     : sv.base+05   // Currently selected input stream
sv.curout    : sv.base+06   // Currently selected output stream
sv.errflag   : sv.base+07   // Internal error flag
sv.absent    : sv.base+08   // Undefined global error handler
sv.lowcode   : sv.base+09   // Byte address of start of code PSECTs
sv.highcode  : sv.base+10   // Byte address of end of code PSECTs

sv.stchain   : sv.base+14   // Head of STATIC name chain

sv.wrch      : sv.base+29   // Secret copy of 'wrch'
$)

MANIFEST $(   // Various instruction fragments
i.addl3       = #XC1   // ADDL3 instruction
i.jsb         = #X16   // JSB instruction
i.pushl       = #XDD   // PUSHL instruction
m.imd         = #X8F   // immediate mode
i.incl        = #XD6   // INCL instruction
i.movl        = #XD0   // MOVL instruction
m.relfpbdef   = #XBD   // FP-relative, byte displacement deferred mode
m.relfpwdef   = #XDD   // FP-relative, word displacement deferred mode
m.relfpldef   = #XFD   // FP-relative, longword displacement deferred mode
m.relpcw      = #XCF   // PC-relative, word displacement mode
m.relpcl      = #XEF   // PC-relative, longword displacement mode
m.relpcwdef   = #XDF   // PC-relative, word displacement deferred mode
m.relpcldef   = #XFF   // PC-relative, longword displacement deferred mode
m.r0reg       = #X50   // R0 register mode
m.fpreg       = #X5D   // FP register mode
m.spreg       = #X5E   // SP register mode
$)

// End of file RTSHDR


